The present invention relates generally to magnetic memory devices, and, more particularly to a method and apparatus for selecting a rowline within a magnetic memory device.
A typical MRAM device includes a plurality of planes of memory cells. Each plane of memory cells is divided into rowlines and bit lines. Rowlines, also termed word lines, extend along the rows of the memory cells and bit lines extend along the columns of the memory cells. A bit of information is stored as a resistance value at the intersection of a rowline and a column. The resistance value depends on the orientation of magnetization. The orientation of magnetization will be one of two stable orientations at a given time. These two orientations, parallel and anti-parallel, represent the logical values xe2x80x9c1xe2x80x9d and xe2x80x9c0.xe2x80x9d The orientation of magnetization of a memory cell can be changed by supplying a current to the rowline and bitline intersecting at the selected memory cell. The currents create magnetic fields, that when combined, can switch the orientation of magnetization of a memory cell from parallel to anti-parallel or vice versa.
As shown in FIG. 1 an MRAM rowline select circuit may employ rowline select circuits 110 and 120 at each end of a rowline. When a memory cell on rowline 100 is accessed, each rowline select circuit 120 determines if that side of the rowline 100 should be connected to ground, voltage source 126 or left floating. This determination is made for each rowline 100, 220, 230 and 240. In addition, each rowline select circuit 110, one of which is connected to the other side of every rowline 100, 220, 230 and 240 in every plane, determines whether the other side of rowline 100 should be connected to current supply 116 or left floating.
Rowline select circuit 120 receives two addressing signals (Add1 and Add2), a WRITE signal and a plane select (PS) signal as inputs. The first addressing signal (Add1) is the output of an address decoding circuit which decodes a portion of the address of the desired rowline. For example, if each plane is broken up into groups of 16 rowlines, the four least significant bits of the address would be fed into the address decoding circuit who""s output is the ADD1 signal. The remaining bits of the address are input into another address decoding circuit who""s output is the ADD2 signal. If both the ADD1 and ADD2 signals indicate a match, then rowline 100 is the desired rowline. Alternatively, a single address decoding circuit can be used to decode the entire address and NOR gate 125 can be removed from circuit 120, however the approach described above uses wires more economically. The WRITE signal indicates whether the desired memory cell should be written to or read from. The plane select signal (PS) selects one of a plurality of planes of cells in a memory array.
In rowline select circuit 120 and 110, the ADD and ADD2 signals are active-low (e.g. when the input is a match, the address decoding circuits output a 0). If the address decoding circuits output active-high signals, the NOR gates 124, 125 and 115 and NAND gate 114 can be replaced with OR gates and an AND gate to achieve the same functionality.
The first addressing signal (ADD1) and the second addressing signal are input into NOR gate 125. The output of NOR gate 125 is coupled to the gate of transistor 123 which, when turned on, selectively couples transistor 121 to ground. The output of NOR gate 125 and the WRITE signal are input into NOR gate 124. The output of NOR gate 124 is coupled to the gate of transistor 122 which, when turned on, selectively couples voltage supply 126 to transistor 121. The plane select signal is coupled to the gate of transistor 121 which, when turned on, selectively couples rowline 100 to a node between transistors 122 and 123.
Rowline select circuit 110 also receives a WRITE signal, a first addressing signal (ADD1), a second addressing signal (ADD2) and a plane select (PS) signal as inputs. The first addressing signal (ADD1) and the Second addressing signal (ADD2) are input into NOR gate 115. The output of NOR gate 115 is input to NAND gate 114 along with the WRITE signal. The output of NAND gate 114 is input to inverter 113, the output of which is applied to the gate of transistor 112. Transistor 112, when turned on by an output signal from inverter 113, selectively connects current supply 116 to transistor 111. Transistor 111 selectively connects the current from current source 116 passing through transistor 112 to rowline 100 when the plane select signal (PS) is activated.
The various states of circuits 120 and 110 are illustrated in FIG. 4. The only important combinations of the first addressing signal (ADD1), the second addressing signal (ADD2), the WRITE signal, and the plane select (PS) signal are when the first addressing signal (ADD1), the second addressing signal (ADD2) and the plane select signal are all active and when the first addressing signal (ADD1), the second addressing signal (ADD2), the WRITE signal and plane select (PS) signal are all active. The remaining possible combinations either do not occur or are not significant to the operation of circuits 120 and 110.
When the first addressing signal (ADD1) and the second addressing signal (ADD2) are active and the WRITE signal is inactive, a read is taking place on rowline 100. When the first and second addressing signals are active (the signals are low), the state of the WRITE signal is inconsequential to circuit 120. When both addressing signals (ADD1 and ADD2) are active, NOR gate 125 will output a high signal. This output signal will activate transistor 123 (connecting rowline 100 to ground when the PS signal is active) as well as insure that NOR gate 124 outputs a low signal deactivating transistor 122. In addition, circuit 110 leaves the right side floating regardless of the plane select (PS) signal because during a read, the WRITE signal is low causing NAND gate 114 to output a high signal, NOT gate 113 to output a low signal and, as a result, transistor 112 is deactivated. This allows a circuit at the end of a column in the same plane as rowline 100 to determine the orientation of magnetization of a memory cell in rowline 100 based on the resistance.
When the first addressing signal (ADD1), the second address signal (ADD2), the WRITE signal and plane select (PS) signal are all active, a write is taking place on rowline 100. Circuit 120 connects the left side of rowline 100 to ground if the plane select (PS) signal is active and leaves the left side of rowline 100 floating if the plane select (PS) signal is inactive. When both addressing signals (ADD1 and ADD2) are active (the signals are low), NOR gate 125 outputs a high signal activating transistor 123 which connects rowline 100 to ground. In addition, NOR gate 115 outputs a high signal, which, in conjunction with an active WRITE signal, causes NAND gate 114 to output a low signal and NOT gate 113 to output a high signal. This activates transistor 112. Consequently, circuit 110 connects the right side of rowline 100 to current supply 116 if the plane select (PS) signal is active and leaves the right side of rowline 100 floating if the plane select signal is inactive. As a result, for a write to a selected rowline 100 in a selected plane, current flows across rowline 100. In conjunction with a current flowing in the column in the same plane as rowline 100, which may be a current for programming a zero or an opposite current for programming a one, the orientation of magnetization of the memory cell at the intersection of the selected row and column can be changed.
A MRAM device 300, as shown in FIG. 3, is typically connected over a bus to a processor 310. The bus can also connect other peripherals to processor 310, such as, for example, I/O devices 320 and hard drive 315. Processor 310 can then access MRAM device 300 to store data as described above.
Due to the relatively high current needed to program a cell, the transistors needed to switch the programming current are considerably larger than transistors used to switch logic signals and they take up more space.
A simplified rowline select circuit which draws less power and consumes less integrated circuit real estate would be desirable.
The present invention mitigates the problems associated with the prior art and provides a unique method and system of selecting a row in a MRAM device on a single end.
In accordance with an exemplary embodiment of the present invention, the rowline select circuit on one side of each rowline is removed and replaced with a transistor connected to one rowline in each plane of memory cells. This transistor connects every rowline to which it is connected to a current supply when a memory cell in any rowline that it is connected to is being read from or written to. The present invention reduces the number of transistors required to activate a rowline, the power consumed by the rowline control circuits as well as the space that the rowline control circuits uses.